Signal Integrity(SI) aware HBM2e/3 interposer design approach considering y-axis offset between logic and HBM die for HPC/AI/Network applications

Abstract

This work demonstrates an efficient signal integrity (SI) aware routing design method considering system-level SI characteristics floor-planning for 2.5D interposer for the AI/HPC/Network solutions in early stage. The proposed method, system-level SI aware interposer design methodology (SSIDM) can accurately estimate the SI characteristics based on limited design information in early stage and even derive a design guideline for efficient SI aware post-layout design process. Using the novel design guidelines provided in this work can help the designer to smoothly transition designs from HBM2e to HBM3 with sufficient SI margins.