The Design of On-the-Fly Virtual Channel Allocation for Low Cost High Performance On-Chip Routers

Abstract

Network-on-Chip (NoC) is an important communication infrastructure for System-on-Chips (SoCs). Designing high performance NoCs with minimized area overhead is becoming a major technical challenge. In this paper, we propose the on-the-fly virtual channel (VC) allocation for low cost high performance on-chip routers. By performing the VC allocation based on the result of switch allocation, the dependency between VC allocation and switch traversal is removed and these stages can be performed in parallel. In this manner, the pipeline of a packet transfer can be shortened in a non-speculative fashion. We have implemented the proposed router on FPGA and evaluated in terms of communication latency, throughput and hardware amount. The experimental results show that, the proposed router with on-the-fly VC allocation reduces the communication latency by 27.3%, and improves throughput by 21.4% as compared to the conventional VC router. In comparison with the look-ahead speculative router, it improves the throughput by 6.2% with 17.6% reduction of area for control logic.