Analytical modelling of SiC MOSFET based on datasheet parameters considering the dynamic transfer characteristics and channel resistance dependency on the drain voltage

Abstract

Silicon Carbide devices enable high power density power electronic converters due to their lower junction capacitances and higher thermal conductivity. Analytical models of these devices help in estimating the switching dynamics, losses and current/voltage stresses on the devices. The dynamics of SiC MOSFET current during turn ON is impacted by the drain voltage it is switched at, due to the drain induced barrier lowering (DIBL) effect. This is however ignored in the existing analytical models available in the literature. This paper thus proposes and develops a new analytical modelling approach that models this effect by relying only on the datasheet parameters, thereby avoiding the need for expensive and time-consuming experimental methods. Dynamic channel resistance is also modelled as a function of drain voltage. The analysis reveals the impact of drain voltage on damping time of high frequency drain current oscillations during turn ON. An experimental double pulse test (DPT) setup using 1.2kV SiC MOSFET (C3MOOI0602K) and Schottky diode (C4D40120D) is built to verify the findings. Further, the accuracy of the proposed model is compared against the most detailed existing model in the literature.