Design and implementation of E1 stream analyzer for CCSS7 protocol

Abstract

The E1 (PCM-30) stream is a European telecommunication standard for communication of data/voice channels in a digital network. This paper deals with the design and implementation of a transparent stream analyzer, capable of handling (up to 2 Mbps) E1 stream and analyzing 30 voice/data channels using an out-of-band common channel signaling system number 7 (CCSS7) protocol. The analyzer is capable of generating an E1 stream and thus can be used for generation, monitoring and blocking of channels. The analyzer can perform analysis and maintenance of E1 (2.048 Mbps) lines. As our analyzer performs the analysis functions in software it is very flexible and can perform many additional features such as algorithms and protocol testing and analysis. The workable synchronous finite state machine (FSM) design of the analyzer is implemented in Verilog and verified on Altera's FLEX10K70 FPGA along with its subsequent interfacing with a PC through an enhanced parallel port