Modelling and comparison of adder designs with Verilog HDL

Abstract

The authors address various forms of adder design commonly encountered in microprocessor design and describe the process of modeling these designs at the gate level using the Verilog hardware description language (HDL). Design and simulation parameters examined in a comparative analysis include design complexity, simulation time, propagation delay effects in adder design, and proper integration of a Verilog based adder description into a complete microprocessor design. Specific adder designs examined include: ripple carry (RC), carry lookahead (CLA), hybrid RC-CLA, single stage carry skip, and carry select adders.