Impacts of Clock Constraints on Side-Channel Leakage of HLS-designed AES Circuits

Abstract

Many IoT devices such as FPGAs are at risk of side-channel attacks. To ensure security, cryptographic circuits such as AES must be implemented on FPGAs. In recent years, technologies to automatically generate RTL circuits from high-level languages such as C/C++ have become popular. In this paper, we design seven AES circuits by high-level synthesis and investigate the relationship between clock constraints and security. T-tests are used to evaluate the security from four metrics. Since the correlation varies depending on the metrics, the circuit design is realized by considering not only security but also circuit performance.