AHB-master controller formal compliance verification

Abstract

In this paper, we use the monitor method to develop a verification intellectual property (VIP) core for Advanced Microcontroller Bus Architecture Advance High-performance Bus (AMBA AHB) compliance verification. The VIP is formulated using System Verilog with assertions, so that it can be used in a simulation-based as well as in formal-based verification methodology. The formal interval property intuitive industrial languages such as Interval Property Language (ITL) and System Verilog Assertion are used to formulate the property set. The Advanced Microcontroller Bus Architecture (AMBA) is an on-chip communications standard for designing highperformance embedded microcontrollers. The operations of based AHB checking (IPC) technique is used to formally verify that the operations of two AHB master controllers comply with the standard. We were able to detect some errors in the AHB master controller.