Configuration Memory Scrubbing of the Xilinx Zynq-7000 FPGA using a Mixed 2-D Coding Technique

Abstract

The paper presents a configuration memory scrubbing approach for the Xilinx Zynq-7000 devices. The approach combines the embedded Error Correction Code of the configuration memory frames and an interframe, interleaved parity scheme to form a mixed two-dimensional (2-D) error correction code. The 2-D coding scheme detects and corrects single and multiple bit upsets in the configuration memory of the Xilinx Zynq-7000 FPGA device. The proposed scrubbing methodology has been evaluated under heavy ion irradiation and achieved 100% error correction coverage.