13.4 A 1GS/s 6-to-8b 0.5mW/Qubit Cryo-CMOS SAR ADC for Quantum Computing in 40nm CMOS

Abstract

Quantum computers (QCs) promise significant speedup for relevant computational problems that are intractable by classical computers. QCs process information stored in quantum bits (qubits) that must be typically cooled down to cryogenic temperatures. Since state-of-the-art QCs employ only a few qubits, those qubits can be driven and read out by room-temperature electronics connected to the cryogenic qubits by only a few wires. However, practical QCs will require more than thousands of qubits, making this approach impractical due to system complexity and reliability concerns. Although frequency multiplexing would reduce the interconnects to room temperature by fitting many qubit channels in the same physical interconnect, an excessive number of interconnects would still be required. An alternative, more scalable solution is a cryogenic electronic interface operating very close to the quantum processor to keep the whole control loop at cryogenic temperature, hence avoiding any high-speed interconnect to room temperature. This system must comprise drivers, readout circuits (LNAs, ADCs), and a digital controller to steer the quantum-algorithm execution [1]. While cryogenic CMOS (cryo-CMOS) wideband drivers and LNAs supporting qubit frequency multiplexing have been shown before [1] –[3], no wideband cryo-CMOS ADC has been demonstrated yet.