Design of a YOLO Model Accelerator Based on PYNQ Architecture

Abstract

The application requirements of object detection models based on deep learning are very extensive. However, high computing power requirements often seriously restrict the application of these models on resource-constrained devices with high energy efficiency requirements. To address this problem, a YOLO model accelerator architecture is proposed based on PYNQ. Based on the FPGA hardware platform, the hardware accelerator is designed by making full use of pipeline, loop unrolling, data reordering and other methods to accelerate the computationally intensive units in the YOLOv2 model such as the convolution and pooling layers. In order to reduce the delay in the data transmission process, the multi-channel transmission architecture combined with the ping-pong buffer is designed, and block-by-block reading strategy is adopted to read the off-chip data. The proposed YOLO model accelerator has been implemented and verified on Xilinx PYNQ-z2 platform. The experimental results show that the system has high detection accuracy and far lower power consumption than CPU and GPU. It can also be deployed on mobile devices to detect the surrounding environment.