Low leakage circuit design using bootstrap technique

Abstract

Leakage power dissipation is drastically increasing with the scaling of the each new technology node. The number of gates per chip has increased for improving the performance of the circuits, rise in operating frequency and many more has resulted in greater leakage power dissipation. That demands low power integrated circuits (ICs). In this paper, bootstrapping technique has been used so as to overcome the leakage power dissipation. 4:1 multiplexer is designed by using bootstrapping technique at 32nm technology node and the results are obtained using Silvaco's tools. The leakage power result obtained had been taken at different voltages (1V, 0.8V, 0.6V, 0.4V) for checking the effect of voltage scaling.