Finfet Standard Cells Delay Model for Fast Timing Analysis

A. Korshunov, V. Khvatov, D. Maksimov
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Abstract

The fast growth of the real projects on FinFET technology has led to the need of design flow changes at all levels of abstraction. Especially interesting for designers is the possibility of early exploration of the FinFET standard cells timings. In this case, it is necessary to take into account the quantification of FinFET channel width, determined by an integer number of fins. The paper presents a model for standard cell delay calculation, which can be used for quick analysis of design options. The linear model allows to calculate the critical path in the circuit without full circuit simulation, using only a small number of empirical parameters. An example of development such model for 20 nm technology is given in the paper.
用于快速时序分析的菲菲特标准单元延迟模型
基于FinFET技术的实际项目的快速增长导致需要在各个抽象层次上改变设计流程。对于设计人员来说,特别有趣的是早期探索FinFET标准单元时序的可能性。在这种情况下,有必要考虑到FinFET通道宽度的量化,由鳍片的整数个数决定。本文提出了一个标准单元延迟计算模型,可用于快速分析设计方案。线性模型允许在没有全电路仿真的情况下计算电路中的关键路径,只使用少量的经验参数。文中给出了该模型在20nm工艺中的开发实例。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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