{"title":"Improvement in Breakdown Voltage of Junctionless Power Transistor with Ga2O3 RESURF region","authors":"M. R., K. S. Nikhil","doi":"10.1109/ICITIIT57246.2023.10068623","DOIUrl":null,"url":null,"abstract":"From the recent reported studies, it is clear that Ga2O3 can offer higher breakdown voltage due to its higher bandgap. However, Ga2O3 based power devices are having challenges like low carrier concentration and less electron mobility. In this article, a Junctionless Enhancement mode Field Effect Transistor (FET) with Ga2O3 REduced SURface Field (RESURF) is proposed. The introduction of n-type Ga2O3 RESURF region between gate and drain region improves the breakdown voltage. The asymmetric gate structure further enhances the breakdown voltage by delaying the attainment of critical electric field. The variation of on resistance (RON) for varying the length of RESURF region (Lr) is also investigated. Junctionless FET with Ga2O3 RESURF has shown large potential for high power integrated circuit applications.","PeriodicalId":170485,"journal":{"name":"2023 4th International Conference on Innovative Trends in Information Technology (ICITIIT)","volume":"23 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2023-02-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2023 4th International Conference on Innovative Trends in Information Technology (ICITIIT)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICITIIT57246.2023.10068623","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0
Abstract
From the recent reported studies, it is clear that Ga2O3 can offer higher breakdown voltage due to its higher bandgap. However, Ga2O3 based power devices are having challenges like low carrier concentration and less electron mobility. In this article, a Junctionless Enhancement mode Field Effect Transistor (FET) with Ga2O3 REduced SURface Field (RESURF) is proposed. The introduction of n-type Ga2O3 RESURF region between gate and drain region improves the breakdown voltage. The asymmetric gate structure further enhances the breakdown voltage by delaying the attainment of critical electric field. The variation of on resistance (RON) for varying the length of RESURF region (Lr) is also investigated. Junctionless FET with Ga2O3 RESURF has shown large potential for high power integrated circuit applications.