A New Generalized Reconfigurable Architecture for Digital Signal Processor

Abstract

In this paper a novel re-configurable digital signal processing (DSP) architecture and algorithm has been proposed where basic building blocks are high performance adders, subtracters, multipliers etc. The architecture has been conceived keeping high performance, low dynamic configuration latency, flexibility and low power consumption in view. Issues involving interconnection among the basic building blocks have been dealt with in details and a new scheme is proposed.