Fault-tolerant 2-D Mesh Network-On-Chip for MultiProcessor Systems-on-Chip

Abstract

Large system-on-chip (SoC) circuits contain increasing number of embedded processor cores while their communication infrastructures are implemented with networks-on-chip (NOC). Due to the increasing transistor and wire densities these circuits are more difficult to test, which requires that different self-diagnosis and self-test methods must be mobilized. Self-diagnosis and self-repair methods usable for invalidating at least minor manufacturing defects of the NOCs may also be needed for improving the chip yield. This paper presents a new fault-tolerant NOC with two-dimensional mesh topology for future multi-processor SoCs (MPSoC). The improved fault-tolerance is implemented with fault-diagnosis-and-repair (FDAR) system, which makes the NOC more testable and diagnosable. The FDAR can detect static, dynamic, and transient faults and repairs the faulty switches. Furthermore, it makes it possible also for the local processors to reconfigure their switch nodes to work correctly. After the reconfigurations a novel adaptive routing algorithm named fault-tolerant dimension-order-routing (FTDOR) is able to route packets adaptively in seriously faulty networks. The usage of the FTDOR makes it also possible to use all of the ports of the edge switch nodes for connecting processors to the NOC, which improves the utilization of the NOC's resources