Design of a Heterogeneous Parallel Processing System for Beam Forming

Abstract

In many defense related applications, very complex hardware and software systems exist. They are characterized by difficult computation and real time requirements. These systems typically have an assorted collection of heterogeneous analog or digital processors. The program that run the embedded system typically is in the order of hundreds of thousands of line of source code. The system is generally very complex, hard to design, and hard to maintain. Due to recent substantial investment and possible pay off in high performance computation by the government it is all natural to examine the possibility of implementing this kind of very complex system on high performance parallel processors. Of the many forms of parallel processor system, distributed heterogeneous parallel system is a possible attractive approach. Despite the continuing research efforts in parallel processing, persistent difficulty and challenge still exists. (1 ) Scalability problem: Measured efficiency of speed up (from benchmarks) experiments with large (=1000’s processing) MIMD parallel architectures are still in the single digit percent range. For vector processors type of supercomputer the performance is a little better in the tenth of percent range. (2) Software parallel processor is still a problem: Programming a paralIel processor system can be done in two different approaches. The first one is to take a regular sequential program and compile i t for a parallel processor system. This is geiierally referred to as the parallelizing compiler approach. The second approach is to recode the program in a parallel language such as LINDA, Fortran 90, or functional (applicative) language. The first approach does not require a large effort of program rewrite. The parallelizing compiler dealing with 1000’s of lines of code does not exist yet, and the available one for small programs still suffers performance problems. The second approach can achieve better performance. However, there is no automatic mapping technology for partitioning and scheduling. Good pedormance in programming parallel processors still relies on slow and tedious manual mapping.