{"title":"High speed 8T SRAM cell design with improved read stability at 180nm technology","authors":"P. Raikwal, V. Neema, A. Verma","doi":"10.1109/ICECA.2017.8212727","DOIUrl":null,"url":null,"abstract":"In this work a novel single-ended 8T static random access memory cell with low power consumption and high read static noise margin is proposed. In the proposed cell to improve read margin differential wordlines are utilized. Additionally during read operation the storing nodes of the cell are totally decoupled from the bit line, which enhances the read capability of the proposed cell. The read static margin of the proposed 8T SRAM cell is 67.37% improved as compare to 6T SRAM cell. The proposed cell saves 41.5% average power during write ‘1’ operation and saves 39.78% power in write ‘0’ operation. During read operation it saves 89.91% power as compare to standard 6T SRAM cell. The proposed 8T SRAM cell shows less propagation delay as compare to conventional 6T SRAM cell.","PeriodicalId":222768,"journal":{"name":"2017 International conference of Electronics, Communication and Aerospace Technology (ICECA)","volume":"2 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2017-04-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"5","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2017 International conference of Electronics, Communication and Aerospace Technology (ICECA)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICECA.2017.8212727","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 5
Abstract
In this work a novel single-ended 8T static random access memory cell with low power consumption and high read static noise margin is proposed. In the proposed cell to improve read margin differential wordlines are utilized. Additionally during read operation the storing nodes of the cell are totally decoupled from the bit line, which enhances the read capability of the proposed cell. The read static margin of the proposed 8T SRAM cell is 67.37% improved as compare to 6T SRAM cell. The proposed cell saves 41.5% average power during write ‘1’ operation and saves 39.78% power in write ‘0’ operation. During read operation it saves 89.91% power as compare to standard 6T SRAM cell. The proposed 8T SRAM cell shows less propagation delay as compare to conventional 6T SRAM cell.