Evolving Embryonic Cell for Combinational Circuits using Cartesian Genetic Programming

Abstract

This research aims to explore the possibility to implement concepts of embryonics with potential of self-repair mechanism. As the field of embryonics (embryo electronics) is based on multi-cellular architecture, the concept of growth from single embryo cell into complete organism can be utilized for fault-tolerant digital circuit design. This paper proposes a novel embryonic fabric and cell architecture that can configure itself as per the circuit requirement. It consists of an embryonic architecture where the configuration data (genome data) is in the form of Cartesian Genetic Programming (CGP). A customized Evolutionary Algorithm (EA) is designed to generate an optimized CGP data for the circuit under design. The CGP data configuration provides the better control at node or gate level in case of circuit fault. The configuration data size in CGP form does not increase linearly with more number of inputs and outputs as in the case of conventional Look Up Table (LUT) form. The embryonic cell architecture proposed is demonstrated for adder and comparator cells. A 4-bit adder is designed using four 1-bit adder cells and a 8-bit comparator is designed using four 2-bit comparator cells by employing cloning mechanism. A 4-bit adder needs 28 bits in LUT form of configuration data, while 45 bits are needed in CGP form. Similarly a 8-bit comparator needs 216 bits in LUT form, while 108 bits are needed in CGP configuration data form. The transfer of signals between cells is through embryonic switch boxes. The design is simulated and tested using Verilog,