Evolving Embryonic Cell for Combinational Circuits using Cartesian Genetic Programming

Gayatri Malhotra, P. Duraiswamy, J. Kishore
{"title":"Evolving Embryonic Cell for Combinational Circuits using Cartesian Genetic Programming","authors":"Gayatri Malhotra, P. Duraiswamy, J. Kishore","doi":"10.1109/CONECCT52877.2021.9622686","DOIUrl":null,"url":null,"abstract":"This research aims to explore the possibility to implement concepts of embryonics with potential of self-repair mechanism. As the field of embryonics (embryo electronics) is based on multi-cellular architecture, the concept of growth from single embryo cell into complete organism can be utilized for fault-tolerant digital circuit design. This paper proposes a novel embryonic fabric and cell architecture that can configure itself as per the circuit requirement. It consists of an embryonic architecture where the configuration data (genome data) is in the form of Cartesian Genetic Programming (CGP). A customized Evolutionary Algorithm (EA) is designed to generate an optimized CGP data for the circuit under design. The CGP data configuration provides the better control at node or gate level in case of circuit fault. The configuration data size in CGP form does not increase linearly with more number of inputs and outputs as in the case of conventional Look Up Table (LUT) form. The embryonic cell architecture proposed is demonstrated for adder and comparator cells. A 4-bit adder is designed using four 1-bit adder cells and a 8-bit comparator is designed using four 2-bit comparator cells by employing cloning mechanism. A 4-bit adder needs 28 bits in LUT form of configuration data, while 45 bits are needed in CGP form. Similarly a 8-bit comparator needs 216 bits in LUT form, while 108 bits are needed in CGP configuration data form. The transfer of signals between cells is through embryonic switch boxes. The design is simulated and tested using Verilog,","PeriodicalId":164499,"journal":{"name":"2021 IEEE International Conference on Electronics, Computing and Communication Technologies (CONECCT)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2021-07-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2021 IEEE International Conference on Electronics, Computing and Communication Technologies (CONECCT)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/CONECCT52877.2021.9622686","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 1

Abstract

This research aims to explore the possibility to implement concepts of embryonics with potential of self-repair mechanism. As the field of embryonics (embryo electronics) is based on multi-cellular architecture, the concept of growth from single embryo cell into complete organism can be utilized for fault-tolerant digital circuit design. This paper proposes a novel embryonic fabric and cell architecture that can configure itself as per the circuit requirement. It consists of an embryonic architecture where the configuration data (genome data) is in the form of Cartesian Genetic Programming (CGP). A customized Evolutionary Algorithm (EA) is designed to generate an optimized CGP data for the circuit under design. The CGP data configuration provides the better control at node or gate level in case of circuit fault. The configuration data size in CGP form does not increase linearly with more number of inputs and outputs as in the case of conventional Look Up Table (LUT) form. The embryonic cell architecture proposed is demonstrated for adder and comparator cells. A 4-bit adder is designed using four 1-bit adder cells and a 8-bit comparator is designed using four 2-bit comparator cells by employing cloning mechanism. A 4-bit adder needs 28 bits in LUT form of configuration data, while 45 bits are needed in CGP form. Similarly a 8-bit comparator needs 216 bits in LUT form, while 108 bits are needed in CGP configuration data form. The transfer of signals between cells is through embryonic switch boxes. The design is simulated and tested using Verilog,
用笛卡儿遗传规划进化胚胎细胞组合电路
本研究旨在探索胚胎学概念实现自我修复机制的可能性。由于胚胎学(胚胎电子学)是一个基于多细胞结构的领域,从单个胚胎细胞发育成完整有机体的概念可以用于容错数字电路的设计。本文提出了一种新的胚胎结构和细胞结构,可以根据电路的要求进行自我配置。它由一个胚胎架构组成,其中配置数据(基因组数据)以笛卡尔遗传规划(CGP)的形式存在。设计了一种自定义进化算法(EA),为所设计的电路生成优化的CGP数据。当电路发生故障时,CGP数据配置提供了更好的节点或门级控制。CGP形式中的配置数据大小不像传统的查找表(lookup Table, LUT)形式那样随着输入和输出数量的增加而线性增加。提出的胚胎细胞结构证明了加法器和比较器细胞。利用克隆机制,利用4个1位加法器单元设计了4位加法器,利用4个2位比较器单元设计了8位比较器。4位加法器需要28位LUT形式的配置数据,而45位CGP形式的配置数据。类似地,8位比较器在LUT形式中需要216位,而在CGP配置数据形式中需要108位。细胞间的信号传递是通过胚胎开关箱进行的。使用Verilog对该设计进行了仿真和测试。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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