{"title":"Rapid prototyping hardware platforms for the development and testing of OFDM based communication systems","authors":"Craig Jamieson, S. Melvin, J. Ilow","doi":"10.1109/CNSR.2005.51","DOIUrl":null,"url":null,"abstract":"Implementation of modern digital transceivers requires an expertise in numerous fields. Conventional transceiver design methods are no longer sufficient to guarantee a fast conversion from initial concept to final product. Moreover, in the testing phase, system simulations alone cannot provide the full insight into the system parameters and performance, especially at the RF stages, where the modeling of power amplifier non-linearities is a highly complex task. To address these design gaps, this paper utilizes software radio solutions. Specifically, it elaborates on transceiver architectural methods at the baseband involving hardware/software partitioning, as well as automatic digital signal processing (DSP) coding strategies that allow for rapid prototyping, testing and verification of algorithms developed in the design simulation stages. In particular, DSP processor and field programmable gate array (FPGA)-based testbeds are described that offer different advantages in the transceiver rapid prototyping methodology. These testbeds were designed to eventually be used in experiments geared towards demonstrating the effectiveness of compensation algorithms for wireless systems like wireless local area network (WLAN) and digital audio broadcasting (DAB), where orthogonal frequency division multiplexed (OFDM) signaling is deployed.","PeriodicalId":166700,"journal":{"name":"3rd Annual Communication Networks and Services Research Conference (CNSR'05)","volume":"52 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2005-05-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"10","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"3rd Annual Communication Networks and Services Research Conference (CNSR'05)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/CNSR.2005.51","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 10
Abstract
Implementation of modern digital transceivers requires an expertise in numerous fields. Conventional transceiver design methods are no longer sufficient to guarantee a fast conversion from initial concept to final product. Moreover, in the testing phase, system simulations alone cannot provide the full insight into the system parameters and performance, especially at the RF stages, where the modeling of power amplifier non-linearities is a highly complex task. To address these design gaps, this paper utilizes software radio solutions. Specifically, it elaborates on transceiver architectural methods at the baseband involving hardware/software partitioning, as well as automatic digital signal processing (DSP) coding strategies that allow for rapid prototyping, testing and verification of algorithms developed in the design simulation stages. In particular, DSP processor and field programmable gate array (FPGA)-based testbeds are described that offer different advantages in the transceiver rapid prototyping methodology. These testbeds were designed to eventually be used in experiments geared towards demonstrating the effectiveness of compensation algorithms for wireless systems like wireless local area network (WLAN) and digital audio broadcasting (DAB), where orthogonal frequency division multiplexed (OFDM) signaling is deployed.