{"title":"Cloud services using hardware accelerators: The case of handwritten digits recognition","authors":"E. Bougioukou, N. Toulgaridis, T. Antonakopoulos","doi":"10.1109/MOCAST.2017.7937620","DOIUrl":null,"url":null,"abstract":"In the era of cloud computing and storage, high performance servers are used for achieving improved accuracy in various application areas. Although local processing is viable in many cases, collecting data from multiple sources and processing them in a server results to optimum parameters estimation for achieving the best possible performance in terms of accuracy. In this work, we present the case of a high performance computing engine for detecting the correct values of handwritten digits. The system exploits a hardware accelerator that implements multiple neural networks for digit recognition and the whole system architecture is presented. Experimental results demonstrate the performance of the implemented system using a Power8 server and a PCIe hardware accelerator.","PeriodicalId":202381,"journal":{"name":"2017 6th International Conference on Modern Circuits and Systems Technologies (MOCAST)","volume":"39 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2017-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"4","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2017 6th International Conference on Modern Circuits and Systems Technologies (MOCAST)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/MOCAST.2017.7937620","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 4
Abstract
In the era of cloud computing and storage, high performance servers are used for achieving improved accuracy in various application areas. Although local processing is viable in many cases, collecting data from multiple sources and processing them in a server results to optimum parameters estimation for achieving the best possible performance in terms of accuracy. In this work, we present the case of a high performance computing engine for detecting the correct values of handwritten digits. The system exploits a hardware accelerator that implements multiple neural networks for digit recognition and the whole system architecture is presented. Experimental results demonstrate the performance of the implemented system using a Power8 server and a PCIe hardware accelerator.