Stateful OpenFlow: Hardware proof of concept

S. Pontarelli, M. Bonola, G. Bianchi, A. Capone, C. Cascone
{"title":"Stateful OpenFlow: Hardware proof of concept","authors":"S. Pontarelli, M. Bonola, G. Bianchi, A. Capone, C. Cascone","doi":"10.1109/HPSR.2015.7483105","DOIUrl":null,"url":null,"abstract":"This paper presents a hardware implementation of Openstate, an extension of OpenFlow that allows performing stateful control functionalities directly inside the switch, without requiring the intervention of an external controller. The paper shows how, with a minimal reworking of the OpenFlow's basic architecture, and reusing the same building blocks, it is possible to greatly extend the intelligence of an OpenFlow switch allowing the offload of many control task directly in the switch. An FPGA based implementation of an Openstate prototype is here presented, the different architectural design choices are discussed, and the performance and limitations of the developed prototype are examinated. Finally, the paper proposes a discussion on the performance achievable by using an ASIC implementation of the OpenState switch1.","PeriodicalId":360703,"journal":{"name":"2015 IEEE 16th International Conference on High Performance Switching and Routing (HPSR)","volume":"273 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2015-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"30","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2015 IEEE 16th International Conference on High Performance Switching and Routing (HPSR)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/HPSR.2015.7483105","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 30

Abstract

This paper presents a hardware implementation of Openstate, an extension of OpenFlow that allows performing stateful control functionalities directly inside the switch, without requiring the intervention of an external controller. The paper shows how, with a minimal reworking of the OpenFlow's basic architecture, and reusing the same building blocks, it is possible to greatly extend the intelligence of an OpenFlow switch allowing the offload of many control task directly in the switch. An FPGA based implementation of an Openstate prototype is here presented, the different architectural design choices are discussed, and the performance and limitations of the developed prototype are examinated. Finally, the paper proposes a discussion on the performance achievable by using an ASIC implementation of the OpenState switch1.
有状态OpenFlow:概念的硬件证明
本文介绍了Openstate的硬件实现,它是OpenFlow的扩展,允许直接在交换机内部执行有状态控制功能,而不需要外部控制器的干预。本文展示了如何通过对OpenFlow的基本架构进行最小程度的重新设计,并重用相同的构建块,从而可以极大地扩展OpenFlow交换机的智能,从而允许直接在交换机中卸载许多控制任务。本文介绍了一种基于FPGA的开放状态原型的实现,讨论了不同的架构设计选择,并对所开发的原型的性能和局限性进行了检查。最后,本文讨论了使用ASIC实现OpenState交换机所能达到的性能。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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