Design and analysis of surge protection circuit in the memory architecture of FeRAM

Abstract

The frequent occurrences of surge current[1] of memory architecture in FeRAM, and the lack of necessary formula derivation in related researches of FeRAM are main aspects of what this work focuses. Therefore, the surge protection circuit is designed and simulated by this work with solid memory architecture of FeRAM to decrease the surge current and average power consumption creatively. The surge protection circuit is composed of a MOSFET and an RC delay circuit, which forces the generation of the surge current to be slowed down by mandatory precharge of the capacitor. On the other hand, necessary circuit analysis and formula derivation are concluded to predict the DC operating point of sensitive amplifier and build a clearly defined limits of operating voltage and the ratio of the maximum ferroelectric capacitance and bitline capacitance in the read/write operation of FeRAM.