Analyzing security vulnerabilities of three-dimensional integrated circuits

Jaya Dofe, Qiaoyan Yu
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Abstract

Despite the well-understood advantages over 2D ICs, three-dimensional integrated circuits (3D ICs) introduce unique and unexplored challenges on managing hardware security. Existing works leverage the 3D structure to address the security concerns in 2D ICs, rather than studying the security threats originated from the 3D integration itself. To fill in this gap, this work analyzes new security threats on 3D ICs by examining five attack scenarios in the supply chain of 3D chips. With special emphasis on inter-die communication, we first model three types of Through Silicon Via (TSV) based hardware Trojans. Our case studies show that the impact of TSV-based Trojans on circuit power and delay can be significant enough to sabotage the integrity and security of 3D ICs. Furthermore, we envision that cross-tier hardware Trojan may become a unique hardware Trojan in 3D ICs to cause bandwidth depletion or information leakage among the tiers.
三维集成电路安全漏洞分析
尽管三维集成电路(3D ic)比2D集成电路具有众所周知的优势,但它在管理硬件安全方面引入了独特且未探索的挑战。现有的工作利用3D结构来解决2D集成电路中的安全问题,而不是研究来自3D集成本身的安全威胁。为了填补这一空白,本研究通过研究3D芯片供应链中的五种攻击场景,分析了3D集成电路的新安全威胁。特别强调芯片间通信,我们首先模拟三种类型的通过硅通孔(TSV)的硬件木马。我们的案例研究表明,基于tsv的木马对电路功率和延迟的影响可能足以破坏3D集成电路的完整性和安全性。此外,我们设想跨层硬件木马可能成为3D ic中唯一的硬件木马,从而导致各层之间的带宽消耗或信息泄漏。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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