{"title":"Design of high-speed errors-and-erasures Reed-Solomon decoders for multi-mode applications","authors":"Y. Lu, Ming-Der Shieh, W. Kuo","doi":"10.1109/VDAT.2009.5158129","DOIUrl":null,"url":null,"abstract":"A multi-mode Reed-Solomon (RS) decoder design based on the reformulated inversionless Berlekamp-Massey (riBM) algorithm is proposed to correct both errors and erasures for any RS code including shortened codes. Without degrading the resulting performance, we effectively improve the hardware utilization of decoder and simplify the routing network in conventional multi-mode decoder design. With the developed multi-mode arrangement, the proposed decoder possesses not only high-performance property but also simple and regular interconnect topology, making the decoder suitable for VLSI realization. Experimental results reveal that for code words of length n ≤ 255 with ν errors and ρ erasures correcting capability, 0≤ 2ν+ρ ≤ 16, the achievable throughput rate of the proposed decoder, implemented in TSMC 0.13µm 1P8M process, is 4Gbps at a maximum operating clock of 450MHz and the total gate count is 50K.","PeriodicalId":246670,"journal":{"name":"2009 International Symposium on VLSI Design, Automation and Test","volume":"1 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2009-04-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"3","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2009 International Symposium on VLSI Design, Automation and Test","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VDAT.2009.5158129","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 3
Abstract
A multi-mode Reed-Solomon (RS) decoder design based on the reformulated inversionless Berlekamp-Massey (riBM) algorithm is proposed to correct both errors and erasures for any RS code including shortened codes. Without degrading the resulting performance, we effectively improve the hardware utilization of decoder and simplify the routing network in conventional multi-mode decoder design. With the developed multi-mode arrangement, the proposed decoder possesses not only high-performance property but also simple and regular interconnect topology, making the decoder suitable for VLSI realization. Experimental results reveal that for code words of length n ≤ 255 with ν errors and ρ erasures correcting capability, 0≤ 2ν+ρ ≤ 16, the achievable throughput rate of the proposed decoder, implemented in TSMC 0.13µm 1P8M process, is 4Gbps at a maximum operating clock of 450MHz and the total gate count is 50K.