Design of 3 stage low noise operational amplifier

Abstract

In this paper a high gain low noise Op-Amp has been designed. In designing of a high gain Op-Amp, for large values of coupling capacitor, gain will decrease. Since our requirement was to increase the gain, so we have designed a three stage Op-Amp. Our designed circuit provides gain of 78.4 dB, which is very much larger than two stage Op-Amp. There is a trade-off between various parameters like Phase margin, gain, slew rate etc. For example, to achieve larger values of GBW, PM will decrease. We have compared the results for two values of input common mode range. Improvement in the designed circuit is done to achieve the desired GBW by recalculating the transistor's W/L ratios and then simulating the results. Gain Bandwidth product of 176.9 MHz and Phase Margin greater than 60 degrees is achieved but at the cost of power dissipation and area. The Op-Amp is designed in gpdk 180 nm CMOS technology.