A Simple Novel Idle Slot Prediction and Avoidance Scheme Using Prediction Bits for DFSA in RFID

Abstract

Idle slots cause identification inefficiency in Aloha-based RFID algorithms. An idle slot prediction and elimination technique is proposed. The algorithm is dubbed idle predicting dynamic frame-slotted Aloha (IP-DFSA). In IP-DFSA, the reader reads a slot for RN16 as well as the idle prediction bits. Using only a few prediction bits, IP-DFSA can predict and eliminate a significant number of successive idle slots following the current time slot. Whereas previous schemes only achieve 36% efficiency on average, simulation results show that IP-DFSA with 1, 2, 3, and 4 idle slot prediction bits achieves 45%, 52.5%, 56%, and 60% system efficiencies, with 83%, 86%, 88%, and 89% time efficiencies, respectively. The system efficiencies of IP-DFSA range from 9% higher to 24% higher than previous schemes for 1 prediction bit to 4 prediction bits. The number k of idle prediction bits is optimized, and it is revealed that koptimal=4 for tag numbers n$\geq$6.