A multilevel DRAM with hierarchical bitlines and serial sensing

Abstract

We propose a multilevel DRAM (MLDRAM) with serial sensing that has lower area overhead than designs that use single-step, flash conversion sensing. The new design exploits hierarchical, multidivided bitlines to offset the reduction in noise margins caused by multilevel signaling and thereby better preserve the signal-to-noise ratio. The multiple sensing operations required to recover multilevel data are performed serially to re-use sense amplifiers and hence minimize the area overhead of the peripheral circuitry at the cost of increased total read time. In a variation of the proposed design, a subset of the addressed row of cells is read in one sensing step while the remaining cells are recovered later in further sensing steps.