High-Speed FPGA-Based Ethernet Traffic Generator

Abstract

New generation networks are facing ever greater demands. When testing new network devices that must process packets at extremely high rates, it is essential to test their functionality and desired performance under maximum traffic load. As a result, in order to test the hardware, a traffic generator is required. This paper proposes an affordable and extensible high-speed FPGA-based Ethernet traffic generator. The proposed solution is able of fully utilizing a 40GbE link, with the possibility of manipulating traffic characteristics at the level of an individual packet. Although intended to run on the DE10-Pro system, the proposed design is portable to other FPGA boards with minimal development effort and changes.