Bridge the gap between simulation and test: An OSA-compliant Virtual Test Environment

Abstract

Virtual Test (VT) is a promising technique that facilitates test development and cuts time-to-market especially for analog/mixed-signal/RF devices. While the concept has been around for more than a decade and its benefits are widely acknowledged, to date it has not become a standard technique in the day-to-day business of test development. The major difficulties are: weak integration between test environment and simulation environment, lack of flexible and sophisticated simulation library for test resource and insufficient simulation efficiency. The paper discusses solutions for addressing the gaps and presents a platform independent - yet easy integrateable Virtual Test Environment (VTE). It is achieved by following steps: first, OSA-compliance - using industry standards with wide acceptance including data format, service API and protocols to pave the way for easy integration. Second, achieving interaction with the test program by modeling test resources with software control interface, this allows simulation models to be dynamically assembled together and exchanging information with the test program during run-time. At last, modeling optimization - the models of test resources in our VTE have different abstraction levels supporting both static and dynamic assembly during dynamic test program execution. Analysis is performed with respect to accuracy vs. efficiency during model assembling phase to cut computational burden. In the end, a seamless integration of VT approach into test development flow is explained.