J. Schlussler, J. Werner, J. Dohndorf, I. Koren, U. Ramacher, Chang-Han Yi, H. Klar
{"title":"Current mode implementation of a neural algorithm for image preprocessing","authors":"J. Schlussler, J. Werner, J. Dohndorf, I. Koren, U. Ramacher, Chang-Han Yi, H. Klar","doi":"10.1109/MNNFS.1996.493779","DOIUrl":null,"url":null,"abstract":"In this article first activities on circuit implementation of analog neural network hardware are presented. These circuits are intended to be used as sensory and preprocessing components of a digital VLSI high level image processing system. The one approach described here is based on the implementation of the McCulloch Pitts neuron model in a current mode circuit technique. A test chip with reduced resolution is being prepared. Simulation results obtained by solving the system of differential equations numerically shows some features of this type of neural network.","PeriodicalId":151891,"journal":{"name":"Proceedings of Fifth International Conference on Microelectronics for Neural Networks","volume":"29 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1996-02-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"3","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of Fifth International Conference on Microelectronics for Neural Networks","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/MNNFS.1996.493779","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 3
Abstract
In this article first activities on circuit implementation of analog neural network hardware are presented. These circuits are intended to be used as sensory and preprocessing components of a digital VLSI high level image processing system. The one approach described here is based on the implementation of the McCulloch Pitts neuron model in a current mode circuit technique. A test chip with reduced resolution is being prepared. Simulation results obtained by solving the system of differential equations numerically shows some features of this type of neural network.