Design of Hybrid Glitch-Reduction Techniques for Loop Unrolled SIMON Block Cypher

Abstract

The growing demand for the Internet of Things in the application fields with minimum latency requirements is emerging at a rapid rate. Securing these applications not only requires the design of lightweight crypto primitives with minimal code footprint but with shorter execution times. However, despite being a vital performance indicator for deterministic time-bound applications, this has not received much attention and has often been sub-prioritised. Low-latency block cyphers employing loop unrolling design techniques are a favourable choice for securing real-time IoT applications. However, although loop unrolling increases the speed of the overall design, glitches between the unrolled round functions increase its dynamic power and energy consumption, making the cyphers unfit for low-power IoT devices. In this paper, the hybrid glitch-reduction techniques designed using different combinational and sequential circuits have been proposed. These techniques have been devised for the SIMON block cypher because of its hardware efficiency. Furthermore, the high-speed loop unrolling technique for SIMON64/128 block cypher has been analysed for low-latency behaviour in light of various trade-offs between different design metrics. These techniques have been simulated and analysed in Xilinx ISE for Artix-7 and Spartan-6 FPGA boards regarding various metrics such as power, area, latency, throughput and critical path. The results demonstrate that the proposed approaches for SIMON64/128 block cypher produces better results certifying their use for high-speed IoT applications.