A low-voltage fully differential CMOS high-speed sample-and-hold circuit

Proceedings of the 44th IEEE 2001 Midwest Symposium on Circuits and Systems. MWSCAS 2001 (Cat. No.01CH37257) Pub Date : 2001-08-14 DOI:10.1109/MWSCAS.2001.986157

Tsung-Sum Lee, Kai-Ren Hsiao

引用次数: 1

Abstract

A new technique for realizing a low-voltage fully differential CMOS high-speed sample-and-hold (S/H) circuit is presented. The design consideration of the building blocks is described in detailed. Simulation results are given to demonstrate the potential advantage of the new technique.

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一种低压全差分CMOS高速采样保持电路

提出了一种实现低电压全差分CMOS高速采样保持电路的新技术。详细描述了构建模块的设计考虑。仿真结果验证了该方法的潜在优势。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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来源期刊

Proceedings of the 44th IEEE 2001 Midwest Symposium on Circuits and Systems. MWSCAS 2001 (Cat. No.01CH37257)

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