A 0.1-mm2 3-channel area-optimized ΣΔ ADC in 0.16-µm CMOS with 20-kHz BW and 86-dB DR

Abstract

Front-ends for automotive sensors must digitize multiple channels with high resolution while minimizing their silicon area to save costs. Both channel latency and inter-channel gain mismatch must be minimized to be able to serve multiple sensor applications, ranging from ABS to power steering, with the same front-end. The proposed ΣΔ ADC simultaneously digitizes 3 channels, each with a DR of 86 dB over a 20-kHz BW using a 75-MHz clock. Channel latency is <;40 ns and inter-channel gain mismatch is <;0.2%. The ADC occupies only 0.1 mm2 in a 0.16-μm CMOS process. The small area is enabled by channel multiplexing, allowing component sharing among the channels, and by the large oversampling ratio (OSR), allowing for smaller capacitors.