S. Mallick, J. Akhil, A. Dasgupta, R. Kar, D. Mandal, S. Ghoshal
{"title":"Optimal design of 5.5 GHz CMOS LNA using hybrid fitness based adaptive De with PSO","authors":"S. Mallick, J. Akhil, A. Dasgupta, R. Kar, D. Mandal, S. Ghoshal","doi":"10.1109/IEECON.2017.8075890","DOIUrl":null,"url":null,"abstract":"This paper presents a novel approach for the optimal design of a Low Noise Amplifier (LNA) with inductive source degeneration circuit using a novel hybrid optimization technique called fitness based adaptive differential evolution with particle swarm optimization (ADEPSO). The simulation results obtained for the designed LNA confirm the effectiveness of the ADEPSO based approach over PSO in terms of the solution quality, design specifications and design objectives. The optimally designed CMOS LNA circuit implemented in 0.18 μm CMOS technology yields a gain of 22.11 dB and the noise figure of 0.799 dB and the power dissipation of 6.6 mW.","PeriodicalId":196081,"journal":{"name":"2017 International Electrical Engineering Congress (iEECON)","volume":"26 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2017-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"5","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2017 International Electrical Engineering Congress (iEECON)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IEECON.2017.8075890","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 5
Abstract
This paper presents a novel approach for the optimal design of a Low Noise Amplifier (LNA) with inductive source degeneration circuit using a novel hybrid optimization technique called fitness based adaptive differential evolution with particle swarm optimization (ADEPSO). The simulation results obtained for the designed LNA confirm the effectiveness of the ADEPSO based approach over PSO in terms of the solution quality, design specifications and design objectives. The optimally designed CMOS LNA circuit implemented in 0.18 μm CMOS technology yields a gain of 22.11 dB and the noise figure of 0.799 dB and the power dissipation of 6.6 mW.