Building heterogeneous reconfigurable systems with a hardware microkernel

J. Agron, D. Andrews
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引用次数: 19

Abstract

Field Programmable Gate Arrays (FPGAs) have long held the promise of allowing designers to create systems with performance levels close to custom circuits but with a softwarelike productivity for reconfiguring the gates. Unfortunately achieving this promise has been elusive. Modern platform FPGAs are now large enough to support complete heterogeneous Multiprocessor System-On-Chips (MPSoCs), however standardized design flows and programming models for such platforms do not yet exist. To achieve true softwarelike levels of productivity, the design flow and development environment for heterogeneous MPSoCs must resemble that of standard homogeneous systems. In this paper we present a new design flow and run-time system that enables developers to program a heterogeneous MPSoC using standard POSIX-compatible programming abstractions. The ability to use a standard programming model is achieved by using a hardware-based microkernel to provide OS services to all heterogeneous components. This approach makes programming heterogeneous MPSoCs transparent, and can increase programmer productivity by replacing synthesis of custom components with faster compilation of heterogeneous executables. The use of a hardware microkernel provides OS services in an ISA-neutral manner, which allows for seamless synchronization and communication amongst heterogeneous threads.
用硬件微内核构建异构可重构系统
现场可编程门阵列(fpga)长期以来一直承诺允许设计人员创建性能水平接近定制电路的系统,但具有类似软件的生产力,可以重新配置门。不幸的是,实现这一承诺一直难以实现。现代平台fpga现在足够大,可以支持完整的异构多处理器片上系统(mpsoc),但是这种平台的标准化设计流程和编程模型还不存在。为了实现真正的类似软件的生产力水平,异构mpsoc的设计流程和开发环境必须类似于标准的同构系统。在本文中,我们提出了一个新的设计流程和运行时系统,使开发人员能够使用标准的posix兼容编程抽象来编程异构MPSoC。使用标准编程模型的能力是通过使用基于硬件的微内核向所有异构组件提供操作系统服务来实现的。这种方法使异构mpsoc的编程变得透明,并且可以通过用异构可执行文件的更快编译取代自定义组件的合成来提高程序员的工作效率。硬件微内核的使用以isa中立的方式提供OS服务,这允许异构线程之间的无缝同步和通信。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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