Parasitic BJT design consideration in SOI MOSFETs

Abstract

In an n-channel silicon-on-insulator (SOI) MOSFET the accumulation of holes in the floating substrate can lead to the rise of the substrate potential and thus turn on the parastic source-substrate-drain bipolar transistor. To minimize the floating-substrate effect, it is essential to reduce the parasitic bipolar transistor current gain ( beta ). The authors examine the effects of beta on the subthreshold slope and drain breakdown voltage (BV/sub DSS/). The BV/sub DSS/ is improved by reducing beta , and the punch-through currents are well correlated with the results of beta and drain-substrate junction leakage currents. The proposed process to improve BV/sub DSS/ is implemented solely by beta reduction without using any exhausted source/drain engineering process to reduce the multiplication factor. The device with lower beta gives higher substrate-source (base) currents which can effectively reduce the substrate potential.<>