A 0.4V 2.02fJ/conversion-step 10-bit hybrid SAR ADC with time-domain quantizer in 90nm CMOS

Abstract

This paper presents an ultra-low voltage and power efficient 10-bit hybrid successive-approximation register (SAR) analog-to-digital converter (ADC). To reduce the total amount of capacitance and relieve requirement of comparator, we propose a hybrid architecture composed of coarse and fine conversions by 7-bit SAR ADC and 3.5-bit time-domain quantizer, respectively. Using residue voltages generated by coarse ADC and converting it to time-domain, the fine ADC detects the least three bits with 0.5-bit redundancy by Vernier delay structure. At 250KS/s and Nyquist rate input, the ADC prototype fabricated in 90nm CMOS consumes 200nW at 0.4V supply. It achieves a SNDR of 53.7db and a resulting FoM of 2.02-fJ/conv.-step.