Design and verification of LTSSM in USB 3.0 link layer using system verilog

Abstract

The proposed design includes the Link Training and Status State Machine (LTSSM). The LTSSM has both the upstream port and downstream port. The transition between all the 12 link states has been designed and verified. Complex scenarios are covered with multiple cover groups with many cover points. The RTL behavior of the LTSSM in Link Layer is verified using System Verilog and its verification is carried out in Mentor Graphics tool. The proposed verification environment includes the constrained randomization, functional coverage and code coverage. In the proposed system, DUT is subjected to the verification with various coverage metrics such as code coverage, functional coverage, etc. The functional coverage obtained 87.5 percentage by using cover groups.