A Low Power Digitally Assisted Analog Front End for Neural Interface with Optical Reception

Kanishka De, R. Ahmed, Cheng Hao, C. Hutchens
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Abstract

This paper presents the design and implementation of a low power, low noise, digitally assisted analog front end for Micro Neural Interface(MNI) in 180nm CMOS technology used for Neural Spike Detection. The inductively coupled RF power harvested system uses a low power two stage neural amplifier with a mid-Band gain of 59.1 dB with a 3-dB band width(BW) of 0.45 to 8KHz, input referred noise of 8.7µVrms and power consumption of 3.19uW on less than 1V [1]. The central controller operates at 200KHz at 500mV consuming a 33.4nW of power while transmitting 8-bit neural data at 200kbps data rate to the final stage [1]. The simulation results and silicon correlation shows the suitability of the Neural Spike Detection system. Fabrication was carried out in UMC 180nm CMOS.
一种具有光接收的神经接口低功耗数字辅助模拟前端
本文设计并实现了一种低功耗、低噪声、数字辅助模拟的180nm CMOS微神经接口(MNI)前端,用于神经脉冲检测。电感耦合射频功率采集系统采用低功率两级神经放大器,中频段增益为59.1 dB, 3db带宽(BW)为0.45至8KHz,输入参考噪声为8.7 μ Vrms,功耗为3.19uW,电压小于1V[1]。中央控制器工作在200KHz, 500mV,消耗33.4nW的功率,同时以200kbps的数据速率向末级传输8位神经数据[1]。仿真结果和硅相关分析表明了该系统的适用性。在UMC 180nm CMOS上进行制造。
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