{"title":"A Low Power Digitally Assisted Analog Front End for Neural Interface with Optical Reception","authors":"Kanishka De, R. Ahmed, Cheng Hao, C. Hutchens","doi":"10.1109/BIBE.2017.00-72","DOIUrl":null,"url":null,"abstract":"This paper presents the design and implementation of a low power, low noise, digitally assisted analog front end for Micro Neural Interface(MNI) in 180nm CMOS technology used for Neural Spike Detection. The inductively coupled RF power harvested system uses a low power two stage neural amplifier with a mid-Band gain of 59.1 dB with a 3-dB band width(BW) of 0.45 to 8KHz, input referred noise of 8.7µVrms and power consumption of 3.19uW on less than 1V [1]. The central controller operates at 200KHz at 500mV consuming a 33.4nW of power while transmitting 8-bit neural data at 200kbps data rate to the final stage [1]. The simulation results and silicon correlation shows the suitability of the Neural Spike Detection system. Fabrication was carried out in UMC 180nm CMOS.","PeriodicalId":262603,"journal":{"name":"2017 IEEE 17th International Conference on Bioinformatics and Bioengineering (BIBE)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2017-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2017 IEEE 17th International Conference on Bioinformatics and Bioengineering (BIBE)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/BIBE.2017.00-72","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0
Abstract
This paper presents the design and implementation of a low power, low noise, digitally assisted analog front end for Micro Neural Interface(MNI) in 180nm CMOS technology used for Neural Spike Detection. The inductively coupled RF power harvested system uses a low power two stage neural amplifier with a mid-Band gain of 59.1 dB with a 3-dB band width(BW) of 0.45 to 8KHz, input referred noise of 8.7µVrms and power consumption of 3.19uW on less than 1V [1]. The central controller operates at 200KHz at 500mV consuming a 33.4nW of power while transmitting 8-bit neural data at 200kbps data rate to the final stage [1]. The simulation results and silicon correlation shows the suitability of the Neural Spike Detection system. Fabrication was carried out in UMC 180nm CMOS.