Low Power Address Generator using Improvised Clocking Scheme

Abstract

Memories occupy a larger portion of the die area in deep submicron technology. Testing such memories is extremely important in the manufacturing process. Minimizing the test power is necessary as power consumption should not exceed the power constraint of the System-On-Chip. The linear feedback register can be used as an address generator in memories to reduce power consumption. So this paper presents an improvised clocking scheme for the address generator for memory built-in self-test. The modified low-power Linear Feedback Shift Register (LFSR) is used as an address generator or test pattern generator. The new clocking scheme decreases the number of switching activities in the address generator. There is 60% reduction in the switching activity. Address generators are simulated using Xilinx ISE 14.7 & compared results with the conventional LFSR with reference to switching activity & test power.