High performance parallel multiplier using Wallace-Booth algorithm

Abstract

This paper presents an efficient implementation of a VLSI high speed parallel multiplier using the Radix/spl I.bar/4 modified Booth algorithm and the Wallace Tree structure. The design is structured for a n/spl times/m multiplication where n can reach up to 126 bits. The Wallace Tree structure serves to compress the partial product term by a ratio of 3:2. To enhance the speed of operation, carry-look-ahead(CLA) adders are used which is independent on the number of bits of the two operands. An efficient VHDL code was written and successfully simulated and synthesised using Altera's MaxplusII(10.0) and ModelSim3.4 CAD tools.