Architectural Exploration on Racetrack Memories

Abstract

It has become a trend that embedded systems are designed for big data and artificial intelligence applications, which demand the large capacity and high access performance of memory. Racetrack memory (RM) is a novel non-volatile memory with high access performance, high density, and low power consumption. Thus, for data-intensive applications specific embedded systems, RM can meet the requirements of access speed, capacity, and power consumption. However, before accessing data on RM, data in nanowires need to be shifted to align them with read/write port, which is called shift operation. Numerous shift operations cause high latency and energy. In that case, increasing the number of ports or reducing the length of tapes while increasing the number of tape strips can reduce the shift operations. However, these methods may increase the area of RM. In this paper, we aim to explore the appropriate RM configurations. An Explore Pareto-Optimal Configuration(EPOC) technique based on application access pattern is proposed to generate the appropriate RM configurations. Lastly, a simple example is used to analyze the configurations generated by EPOC.