High-speed serial links: design trends and challenges

V. Stojanović
{"title":"High-speed serial links: design trends and challenges","authors":"V. Stojanović","doi":"10.1109/IWSOC.2005.72","DOIUrl":null,"url":null,"abstract":"Summary form only given. In this talk we describe design trends in high-speed serial links from two complementary viewpoints. On one hand we have improvements of the channel through microwave engineering of the passive interconnects/backplanes, and on the other hand a trend toward increased sophistication of the serial link circuits, employing more and more of the communications techniques to compensate for the channel and noise. We describe recent breakthroughs in passive backplane design as well as give some predictions about the capacity of the typical backplane interconnect channels. By looking at the target interconnect applications, like 10-100Tb/s routers, it is clear that both the data rate and power have to improve by an order of magnitude each, to achieve the design goal with manageable physical dimensions of the system. This means an improvement of two orders in magnitude in energy cost per bit, from current designs. We believe that the emerging link design trends like multi-tone signaling and channel-and-circuit-aware coding have the promise to fulfil this task.","PeriodicalId":328550,"journal":{"name":"Fifth International Workshop on System-on-Chip for Real-Time Applications (IWSOC'05)","volume":"40 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2005-07-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Fifth International Workshop on System-on-Chip for Real-Time Applications (IWSOC'05)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IWSOC.2005.72","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 2

Abstract

Summary form only given. In this talk we describe design trends in high-speed serial links from two complementary viewpoints. On one hand we have improvements of the channel through microwave engineering of the passive interconnects/backplanes, and on the other hand a trend toward increased sophistication of the serial link circuits, employing more and more of the communications techniques to compensate for the channel and noise. We describe recent breakthroughs in passive backplane design as well as give some predictions about the capacity of the typical backplane interconnect channels. By looking at the target interconnect applications, like 10-100Tb/s routers, it is clear that both the data rate and power have to improve by an order of magnitude each, to achieve the design goal with manageable physical dimensions of the system. This means an improvement of two orders in magnitude in energy cost per bit, from current designs. We believe that the emerging link design trends like multi-tone signaling and channel-and-circuit-aware coding have the promise to fulfil this task.
高速串行链路:设计趋势与挑战
只提供摘要形式。在这次演讲中,我们将从两个互补的角度描述高速串行链路的设计趋势。一方面,我们通过无源互连/背板的微波工程改善了信道,另一方面,串行链路电路越来越复杂,采用越来越多的通信技术来补偿信道和噪声。我们描述了无源背板设计的最新突破,并对典型背板互连通道的容量进行了一些预测。通过查看目标互连应用程序,如10-100Tb/s路由器,很明显,数据速率和功率都必须分别提高一个数量级,以实现具有可管理的系统物理尺寸的设计目标。这意味着与目前的设计相比,每比特的能源成本提高了两个数量级。我们相信,新兴的链路设计趋势,如多音信号和信道和电路感知编码,有希望完成这一任务。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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