Replacement Policies for a Function-Based Instruction Memory: A Quantification of the Impact on Hardware Complexity and WCET Estimates

Abstract

Instruction memories have a large influence on the timing behavior of hard real-time systems. Thus, to obtain safe and tight WCET estimates the instruction memory has to be predictable. Instruction memories in embedded real-time systems range from scratchpads with fixed content to dynamically managed fine-grained caches. In this paper we focus on a function-based dynamic instruction memory (D-ISP) and examine different replacement policies. We show their influence on the timing behavior of a hard real-time system and the complexity of a hardware implementation. A timing analysis unveils that a stack-based replacement policy reaches similar WCET estimates as LRU, especially for small scratchpad sizes. But in contrast to the stack-based replacement policy, LRU cannot be implemented with a reasonable amount of resources. Whereas, an experimental implementation of the proposed stack-based replacement policy needs only up to 23% more resources than a FIFO implementation.