Design and evaluation of optimized router pipeline stages for network on chip

Abstract

In the past few years, Network on chip (NoC) is presented as the best communication architecture for complex chip. Unlike conventional bus, NoC allows many cores to communicate concurrently, provides more scalability and enhance the system performances. For this reason, we propose a flexible router for NoC architecture. The proposed router implements a minimal routing algorithm to avoid deadlocks and a priority based arbiter to ensure the quality of service (QoS) improvement. In this paper, we optimize a previous version of our router design and present an efficient approach to reduce the dependency between the pipeline stages for NoC architectures. This work aims to reduce the hardware complexity and enhance the system performances. In order to evaluate our design performances we compared it with other popular works from the literature.