A 6bit, 7mW, 250fJ, 700MS/s subranging ADC

Abstract

A 6 bit, 7 mW, 700 MS /s subranging ADC fabricated in 90 nm CMOS technology with SNDR of 34 dB for Nyquist input frequency is presented. The subranging architecture using CDACs, gate-weighted interpolation scheme, and digitally offset calibrating double-tail latched comparators has demonstrated an ultra low FoM of 250 fJ/conv. steps. and attractiveness for embedded IP for low power SoCs.