Detection conditions for errors in self-adaptive better-than-worst-case designs

Abstract

The rapidly increasing variability in circuit performance in highly scaled technologies has given rise to novel “better-than-worst-case” circuit design methods. They aim to overcome worst-case clock timing requirements by employing a shorter clock period and allowing occasional errors to occur; these are detected and recovered from by low-cost error detection and correction techniques. We investigate conditions under which timing error detection based on the memory element duplication with delayed capture is reliable even under extreme variations, where the key problem arises from short-path invalidation mechanisms. We consider two known mitigation techniques: buffer padding and latch placement. The derived conditions can yield the interval of clock periods within which an adaptive frequency scaling strategy may reliably operate. We show that buffer padding is impossible if variability exceeds a certain limit, but latch placement always yields a solution, works for more clock frequencies, and tends to incur less area costs, at the cost of clock power.