Automated test bench generation for high-level synthesis flow ABELITE

Abstract

The paper presents an approach for integration of automatic test bench generation based on a hierarchical test pattern generator Decider into the high-level synthesis flow Abelite. While the high-level synthesis flow provides fast results of complex systems design, functional verification of the design including initial specification has remained until now a sophisticated manual process. The automatically generated test benches provide high code coverage for simulation and are readable for debug. The experiments demonstrate viability and efficiency of the proposed approach.