Novel Congestion-estimation and Routability-prediction Methods based on Machine Learning for Modern FPGAs

Abeer Y. Al-Hyari, Ziad Abuowaimer, T. Martin, G. Grewal, S. Areibi, A. Vannelli
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引用次数: 3

Abstract

Effectively estimating and managing congestion during placement can save substantial placement and routing runtime. In this article, we present a machine-learning model for accurately and efficiently estimating congestion during FPGA placement. Compared with the state-of-the-art machine-learning congestion-estimation model, our results show a 25% improvement in prediction accuracy. This makes our model competitive with congestion estimates produced using a global router. However, our model runs, on average, 291× faster than the global router. Overall, we are able to reduce placement runtimes by 17% and router runtimes by 19%. An additional machine-learning model is also presented that uses the output of the first congestion-estimation model to determine whether or not a placement is routable. This second model has an accuracy in the range of 93% to 98%, depending on the classification algorithm used to implement the learning model, and runtimes of a few milliseconds, thus making it suitable for inclusion in any placer with no worry of additional computational overhead.
基于机器学习的现代fpga拥塞估计和可达性预测新方法
在放置过程中有效地估计和管理拥塞可以节省大量的放置和路由运行时间。在本文中,我们提出了一个机器学习模型,用于准确有效地估计FPGA放置期间的拥塞。与最先进的机器学习拥塞估计模型相比,我们的结果显示预测精度提高了25%。这使得我们的模型与使用全局路由器产生的拥塞估计具有竞争力。然而,我们的模型平均运行速度比全局路由器快291倍。总的来说,我们能够将放置运行时间减少17%,路由器运行时间减少19%。本文还提出了一个额外的机器学习模型,该模型使用第一个拥塞估计模型的输出来确定一个位置是否可路由。第二个模型的准确率在93%到98%之间,这取决于用于实现学习模型的分类算法,其运行时间为几毫秒,因此适合将其包含在任何砂矿中,而无需担心额外的计算开销。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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