C. Ulaganathan, B. Blalock, J. Holleman, C. Britton
{"title":"An ultra-low voltage self-startup charge pump for energy harvesting applications","authors":"C. Ulaganathan, B. Blalock, J. Holleman, C. Britton","doi":"10.1109/MWSCAS.2012.6291993","DOIUrl":null,"url":null,"abstract":"An ultra-low voltage, self-starting, switched-capacitor based charge pump is proposed for energy harvesting applications. The integrated linear charge pump topology presented in this work has been optimized for low-voltage start-up. The control signals for the charge-transfer switches (CTS), generated using two clock phases, reduce reverse currents and thus improve the efficiency of the converter. Adiabatic switching techniques have been employed to reduce the switching losses associated with the CTS gate control. This design has been implemented in a 130-nm CMOS process. Simulation results demonstrate a low startup voltage of 125 mV with efficiency of 62 % for a static current load of 0.1 μA.","PeriodicalId":324891,"journal":{"name":"2012 IEEE 55th International Midwest Symposium on Circuits and Systems (MWSCAS)","volume":"2 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2012-09-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"19","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2012 IEEE 55th International Midwest Symposium on Circuits and Systems (MWSCAS)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/MWSCAS.2012.6291993","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 19
Abstract
An ultra-low voltage, self-starting, switched-capacitor based charge pump is proposed for energy harvesting applications. The integrated linear charge pump topology presented in this work has been optimized for low-voltage start-up. The control signals for the charge-transfer switches (CTS), generated using two clock phases, reduce reverse currents and thus improve the efficiency of the converter. Adiabatic switching techniques have been employed to reduce the switching losses associated with the CTS gate control. This design has been implemented in a 130-nm CMOS process. Simulation results demonstrate a low startup voltage of 125 mV with efficiency of 62 % for a static current load of 0.1 μA.